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How Computers Work

What is a computer? Computers are machines that perform arithmetical calculations automatically, under the control of sequences of instructions, or programs, in their internal storage, or memory.

Computers can be programmed in languages that people find easy to use and understand, but programs in these languages are either read and acted upon (or interpreted) by other computer programs, or translated into the computer's own language (or compiled) by other computer programs.

What does a computer's own language look like?

There are a number of different formats used by different types of computer. The instruction set used by the most popular type of microprocessor is quite complicated, because when it was originally developed as a 16-bit processor, it was designed to be very similar to the 8-bit processor that preceded it; and then new instructions were added on to make it a 32-bit processor.

Thus, as an introduction to computer machine language, a fictitious machine with a simple design is shown here. (It is, however, quite strongly inspired by two real machines: primarily the IBM 360, and to some extent by the Motorola 68000.)

The computer is designed to handle an address space of 4,294,967,296 bytes, because an address occupies 32 bits, and is treated as an unsigned quantity.

Integers are stored in two's complement notation; what this means can be explained by using a decimal computer which uses ten's complement notation, the decimal equivalent, as an example. If a computer stores numbers in only four digits, then adding 9999 to 5, which normally produces 10,004, will instead just produce 4, because the first digit is cut off.

Thus, 9999 can be thought of as standing for -1, without the need to include a sign directly in how numbers are represented.

Similarly, in a computer that stores numbers in only four hexadecimal digits, FFFF stands for -1 in two's complement notation.

Other formats are one's complement notation, where FFFE would be -1, and sign-magnitude notation, where 8001 would be -1.

Our computer would have the following complement of registers directly visible to the ordinary programmer:

where a register is like the display on a pocket calculator; a place where a number is kept with which the computer is currently working.

Eight registers are Arithmetic/Index Registers. They are used for calculations on 32-bit integers, as well as calculations on shorter 16-bit or 8-bit integers. Also, the number in one of these registers can be used by an instruction as an index register; that means the number will indicate which element of an array is to be used for a calculation.

Eight registers are Base Registers. While addresses in this computer are 32 bits long, to allow a large amount of memory to be used, it would be wasteful to include a 32-bit address in every instruction that refers to memory. Instead, instructions that refer to memory give the number of a Base Register, and its 32-bit contents are added to the 16-bit address in the instruction itself to identify the memory location to be used.

Note that the contents of an index register or a base register are both added to the address in an instruction, but they are normally used for opposite purposes. The base register indicates the large area of memory being used; the address in the instruction indicates the particular variable being used; and the index register indicates the element of an array variable.

The ordinary arithmetic instructions of this computer come in the following formats:

Each instruction comes in several parts. The opcode indicates what operation is being performed. It also indicates what kind of number is being operated on. The field marked dR (destination register) indicates which of the eight registers of the appropriate type will contain the result of the operation, and which also contains the first operand for the operation. The fields marked sX and sB indicate the index register and the base register used in calculating the address of the source of the second operand for the operation. If sB is zero, a memory operand is not used; instead, a register is used as the source, and thus sR (source register) replaces sX. If a memory operand is used, but sX is zero, that simply means that indexing does not take place.

The opcodes for these instructions are:

000xxx IB    Insert Byte
001xxx CB    Compare Byte
002xxx LB    Load Byte
003xxx STB   Store Byte
004xxx AB    Add Byte
005xxx SB    Subtract Byte

010xxx NB    AND Byte
011xxx OB    OR Byte
012xxx XB    XOR Byte
013xxx SWB   Swap Byte
014xxx ULB   Unsigned Load Byte
015xxx SBG   Store Byte if Greater

020xxx IH    Insert Halfword
021xxx CH    Compare Halfword
022xxx LH    Load Halfword
023xxx STH   Store Halfword
024xxx AH    Add Halfword
025xxx SH    Subtract Halfword
026xxx MH    Multiply Halfword
027xxx DH    Divide Halfword

030xxx NH    AND Halfword
031xxx OH    OR Halfword
032xxx XH    XOR Halfword
033xxx SWH   Swap Halfword
034xxx ULH   Unsigned Load Halfword

036xxx MEH   Multiply Extensibly Halfword
037xxx DEH   Divide Extensibly Halfword

041xxx C     Compare
042xxx L     Load
043xxx ST    Store
044xxx A     Add
045xxx S     Subtract
046xxx M     Multiply
047xxx D     Divide

050xxx N     AND
051xxx O     OR
052xxx X     XOR
053xxx SW    Swap

056xxx ME    Multiply Extensibly
057xxx DE    Divide Extensibly

061xxx CL    Compare Long
062xxx LL    Load Long
063xxx STL   Store Long
064xxx AL    Add Long
065xxx SL    Subtract Long
066xxx ML    Multiply Long
067xxx DL    Divide Long

070xxx NL    AND Long
071xxx OL    OR Long
072xxx XL    XOR Long
073xxx SWL   Swap Long

076xxx MEL   Multiply Extensibly Long
077xxx DEL   Divide Extensibly Long

111xxx CF    Compare Floating
112xxx LF    Load Floating
113xxx STF   Store Floating
114xxx AF    Add Floating
115xxx SF    Subtract Floating
116xxx MF    Multiply Floating
117xxx DF    Divide Floating

121xxx CD    Compare Double
122xxx LD    Load Double
123xxx STD   Store Double
124xxx AD    Add Double
125xxx SD    Subtract Double
126xxx MD    Multiply Double
127xxx DD    Divide Double

131xxx CQ    Compare Quad
132xxx LQ    Load Quad
133xxx STQ   Store Quad
134xxx AQ    Add Quad
135xxx SQ    Subtract Quad
136xxx MQ    Multiply Quad
137xxx DQ    Divide Quad

It may not be completely obvious what some of these instructions do from their names.

The Byte instructions act on the least significant 8 bits of the arithmetic-index registers. The Halfword instructions act on the least significant 16 bits of the arithmetic-index registers. The instructions which act on an entire arithmetic-index register are those whose name does not mention a type. The Long instructions act on pairs of registers, and thus only even-numbered register operands are possible with them (but any index or base register, even or odd, can still be used).

The Floating instructions use the first 32 bits of the floating-point registers, the Double instructions the first 64 bits, and the Quad instructions use the entire 128 bits.

An Insert instruction loads an operand shorter than the destination register into the last few bits of that register without disturbing the bits which cannot be loaded because the operand is too short in size. In this case, a Load instruction instead causes its operand to be sign extended; that is, if the first bit is 0, all bits to the left of what is being loaded are cleared; if the first bit is 1, all bits to the left are set to 1. In an Unsigned Load instruction, bits beyond the item loaded to the left are always cleared.

The Compare instructions don't change any numbers, but they set status bits as if a subtraction had been performed, except that the subtraction is one performed as if no overflows could take place.

A Multiply Extensibly instruction produces a product that is twice as long as its two operands. The least significant part is stored in the destination register; the most significant part is stored immediately previously. For MEH, that is in the left-hand part of the same register; for ME, that is in the previous register; and for MEL, that is in the previous two registers.

A Divide Extensibly instruction requires an operand that is twice as long as the precision in use to be set up in the same area as the result of a Multiply Extensibly. After the operation, the quotient is in the double-length result area, and the remainder follows in the next register or registers. In the case of Divide Extensibly Halfword, the remainder is in the least significant part of the next register, even though that means there is a 16-bit gap.

The Store Byte if Greater instruction replaces the byte at the address of its memory operand by the byte contained in its register operand only if that byte, treated as an unsigned byte, is greater than the byte at that location; also, status bits are set based on the comparison.

In addition to the standard memory-reference instructions, other types of instruction are required in a computer. Here are the formats of these more specialized instructions:

and here are their opcodes:

101xxx CP    Compare Packed
102xxx MVP   Move Packed

104xxx AP    Add Packed
105xxx SP    Subtract Packed
106xxx MP    Multiply Packed
107xxx DP    Divide Packed

141xxx CC    Compare Character
142xxx MVC   Move Character

1441xx JL    Jump if Low
1442xx JE    Jump if Equal
1443xx JLE   Jump if Low or Equal
1444xx JH    Jump if High
1445xx JNE   Jump if Not Equal
1446xx JHE   Jump if High or Equal
1447xx JMP   Jump

145xxx JMS   Jump to Subroutine
146xxx JXH   Jump if Index High
147xxx JXLE  Jump if Index Low or Equal

150xxx SHL   Shift Left
151xxx SHR   Shift Right

153xxx ASR   Arithmetic Shift Right
154xxx ROL   Rotate Left
155xxx ROR   Rotate Right
156xxx RLC   Rotate Left through Carry
157xxx RRC   Rotate Right through Carry

162xxx LM    Load Multiple
163xxx STM   Store Multiple
164xxx LMBR  Load Multiple Base Registers
165xxx STMBR Store Multiple Base Registers
166xxx LMQ   Load Multiple Quad
167xxx STMQ  Store Multiple Quad

170xxx ECS   Execute Condensed Subroutine

174xxx LBRA  Load Base Register with Address

176xxx LBR   Load Base Register
177xxx STBR  Store Base Register

Some of these instructions involve bits of the status word. There is a carry bit which is set, either to 0 or to 1, by operations that could produce a carry out of one of the 32-bit arithmetic/index registers. Also, other bits indicate if the result of an arithmetic operation, whether integer or floating-point, is positive, negative, or zero. These determine if a conditional jump instruction results in a jump.

If indexed addressing is used in a jump instruction, the instruction does not jump to the memory location at the effective address, but instead to the location whose address it contains. This addressing mode, post-indexed indirect addressing, allows branching to one of several locations in a list. This also applies to the JMS instruction.

The JXH and JXLH instructions decrement and increment, respectively, the count register specified in the cR field, compare it to the limit register specified in the lR field, and jump if the count register is high in the first case, or low or equal in the second.

The LM and STM instructions operate on a range of destination registers specified in the instruction, and are useful for saving and restoring registers when a subroutine is called. The LMBR and STMBR instructions, and the LMQ and STMQ instructions perform the same function for the base registers and the floating-point registers.

The LBR and STBR instructions, as well as the LBRA instruction, have the format of a conventional memory-reference instruction. The LBRA instruction, instead of disturbing the contents of the location it refers to, merely places its address in the base register whose number is indicated by the dR field.

The instruction format shown as "Alternate" applies to the ECS instruction. It is a branch instruction, as can be seen from the presence of a jB (jump base) field. The fields iM and fM have the following significance:

    iM    fM
    00   000    one-byte integer
    01   001    two-byte (halfword) integer
    10   010    four-byte (32-bit) integer
    11   011    eight-byte (64-bit) integer
         100    (not used)
         101    four-byte floating-point number
         110    eight-byte floating-point number
         111    sixteen-byte floating-point number

and the target of the jump is a program written in a condensed-format instruction set in which only a single bit, instead of three bits, specify operand type.

Two instruction formats are available: one where the memory address consists of a single byte, indicating one of 256 operands having the type required for the instruction in a memory area pointed to by base register zero (which is otherwise unused), and one where the source operand is a register, and the destination operand is always register zero.

The two instruction formats used are shown here:

The opcode consists of the last four bits of the seven-bit opcode associated with the instruction type, or the last three bits for floating-point types.

Thus, the opcodes represent the following instructions:

0000 0 IPC  Insert Primary Condensed
0001 0 CPC  Compare Primary Condensed
0010 0 LPC  Load Primary Condensed
0011 0 STPC Store Primary Condensed
0100 0 APC  Add Primary Condensed
0101 0 SPC  Subtract Primary Condensed
0110 0 MPC  Multiply Primary Condensed
0111 0 DPC  Divide Primary Condensed
1000 0 NPC  AND Primary Condensed
1001 0 OPC  OR Primary Condensed
1010 0 XPC  XOR Primary Condensed
1011 0 SWPC Swap Primary Condensed
1100 0 ULPC Unsigned Load Primary Condensed

1110 0 MEPC Multiply Extensibly Primary Condensed
1111 0 DEPC Divide Extensibly Primary Condensed

0000 1 ISC  Insert Secondary Condensed
0001 1 CSC  Compare Secondary Condensed
0010 1 LSC  Load Secondary Condensed
0011 1 STSC Store Secondary Condensed
0100 1 ASC  Add Secondary Condensed
0101 1 SSC  Subtract Secondary Condensed
0110 1 MSC  Multiply Secondary Condensed
0111 1 DSC  Divide Secondary Condensed
1000 1 NSC  AND Secondary Condensed
1001 1 OSC  OR Secondary Condensed
1010 1 XSC  XOR Secondary Condensed
1011 1 SWSC Swap Secondary Condensed
1100 1 ULSC Unsigned Load Secondary Condensed

1110 1 MESC Multiply Extensibly Secondary Condensed
1111 1 DESC Divide Extensibly Secondary Condensed

followed by an additional R for Register where a short-format instruction, occupying a single byte, is to be assembled.

Opcode 1101 indicates several possible operations, depending on the following dR or sR field:

1101 0 000   NOPCR No Operation Condensed Register
                      no operation

1101 0 010 * XNX   Execute Next Indexed

1101 0 100   CLIR  Condensed Long Instructions Register
                      switch to 16-bit instructions
1101 0 101   CSI   Condensed Short Instructions
                      switch to 8-bit instructions
1101 0 111   RCB   Return from Condensed Block
             RCBR  Return from Condensed Block Register
                      return from condensed instruction block

1101 1 nzp * LBC   Loop Back Condensed
                      loop back 0-255 16-bit halfwords if negative/zero/positive

Instructions marked with an asterisk do not require a preceding CLIR instruction, even though they are in 16-bit format, when executed following short format instructions. All except LBC also cause an implied CLIR for the interpretation of following instructions.

The last three bits of the 8-bit operand of the XNX instruction indicate which arithmetic/index register acts as an index register for the following instruction.

Thus, the ECS instruction allows subroutines to be executed which take up less memory than subroutines in the regular instruction set, allowing longer algorithms to fit in cache.

Of course, there are many aspects to the architecture of a computer besides its instruction set.

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